_______ signal is generated by combining RD and WR signals with IO/M
control
memory
register
system
100 practice sets · Page 3 of 5
_______ signal is generated by combining RD and WR signals with IO/M
control
memory
register
system
The remaining address line of ______ bus is decoded to generate chip select signal
data
address
control bus
both (a) and (b)
To interface memory with the microprocessor, connect register the lines of the address bus must be added to address lines of the _______ chip.
single
memory
multiple
triple
Microprocessor provides signal like ____ to indicate the read operatio
LOW
MCMW
MCMR
MCMWR
The ________of the memory chip will identify and select the register for the EPROM
internal decoder
external decoder
address decoder
data decoder
The Microprocessor places 16 bit address on the add lines from that address by _____ register should be selected
address
one
two
three
The Microprocessor places __________ address on the address bus
4 bit
8 bit
16 bit
32 bit
To perform any operations, the Mp should identify the __________
register
memory
interface
system
Primary function of memory interfacing is that the _________ should be able to read from and write into register
multiprocessor
microprocessor
dual Processor
coprocessor
The main concerns of the ___________ are to define a flexible set of commands
memory interface
peripheral interface
both (A) and (B)
control interface
A _____ Instruction at the end of interrupt service program takes the execution back to the interrupted program
forward
return
data
line
The ___ bus controller device decodes the signals to produce the control bus signal
internal
data
external
address
In max mode, control bus signal So,S1 and S2 are sent out in ____________ form
decoded
encoded
shared
unshared
If MN/MX is low the 8086 operates in __________ mode
Minimum
Maximum
both (A) and (B)
medium
In a minimum mode there is a ___________ on the system bus
single
double
multiple
triple
The RD, WR, M/IO is the heart of control for a __________ mode
minimum
maximum
compatibility mode
control mode
The functions of Pins from 24 to 31 depend on the mode in which _______ is operating
8085
8086
80835
80845
________ is used to write into memory
RD
WR
RD / WR
CLK
The address bits are sent out on lines through __________
A16-19
A0-17
D0-D17
C0-C17
The pin of minimum mode AD0- AD15 has _________ data bus
4 bit
20 bit
16 bit
32 bit