The pin of minimum mode AD0-AD15 has ____________ address
16 bit
20 bit
32 bit
4 bit
100 practice sets · Page 4 of 5
The pin of minimum mode AD0-AD15 has ____________ address
16 bit
20 bit
32 bit
4 bit
The ___________ is required to synchronize the internal operands in the processor CLK Signal
UR Signal
Vcc
AIE
Ground
The BIU contains FIFO register of size 6 bytes called _____.
queue
stack
segment
register
The 8086 fetches instruction one after another from __________ of memory
code segment
IP
ES
SS
The _______ contains an offset instead of actual address
SP
IP
ES
SS
The _________ translates a byte from one code to another code
XLAT
XCHNG
POP
PUSH
The microprocessor determines whether the specified condition exists or not by testing the ______
carry flag
conditional flag
common flag
sign flag
The conditional branch instruction specify ___________ for branching
conditions
instruction
address
memory
Instruction providing both segment base and offset address are called _____
below type
far type
low type
high type
The JS is called as ______
jump the signed bit
jump single bit
jump simple bit
jump signal it
_________destination inverts each bit of destination
NOT
NOR
AND
OR
IMUL source is a signed _________
multiplication
addition
subtraction
division
INC destination increments the content of destination by _______
1
2
30
41
LDs copies to consecutive words from memory to register and ___________
ES
DS
SS
CS
The push source copies a word from source to ______
stack
memory
register
destination
The IP is ________ bits in length
8 bits
4 bits
16 bits
32 bits
The CS register stores instruction _____________ in code segment
stream
path
codes
stream line
The DS is called as _______
data segment
digital segment
divide segment
decode segment
The 1 MB byte of memory can be divided into ______ segment
1 Kbyte
32 Kbyte
64 Kbyte
16 Kbyte
The BIU contains FIFO register of size __________ bytes
8
6
4
12