1.
Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________?
A
11
B
00
C
1
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70 practice sets · Page 1 of 4
Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________?
11
00
1
The terminal count of a 3-bit binary counter in the DOWN mode is ________?
111
101
10
The decimal value for E
12
10
14
15
On a J-K flip-flop, when is the flip-flop in a hold condition?
J = 0, K = 0
J = 1, K = 0
J = 0, K = 1
J = 1, K = 1
What is the significance of the J and K terminals on the J-K flip-flop?
There is no known significance in their designations
The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH
The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit
All of the other letters of the alphabet are already in use
The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________
opposite, active clock edge
inverted, positive clock edge
quiescent, negative clock edge
reset, synchronous clock edge
A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
constantly LOW
constantly HIGH
a 20 kHz square wave
a 10 kHz square wave
A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
clock is LOW
slave is transferring
flip-flop is reset
clock is HIGH
A J-K flip-flop is in a "no change" condition when ________
J = 1, K = 1
J = 1, K = 0
J = 0, K = 1
J = 0, K = 0
How is a J-K flip-flop made to toggle?
J = 0, K = 0
J = 1, K = 0
J = 0, K = 1
J = 1, K = 1
What is the significance of the J and K terminals on the J-K flip-flop?
There is no known significance in their designations
The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH and the J input is also HIGH
The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop
All of the other letters of the alphabet are already in use
When both inputs of a J-K flip-flop cycle, the output will:
be invalid
not change
change
toggle
The output of a gated S-R flip-flop changes only if the:
flip-flop is set
control input data has changed
flip-flop is reset
input data has no change
What is one disadvantage of an S-R flip-flop?
It has no enable input
It has an invalid state
It has no clock input
It has only a single output
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________?
SET
RESET
Clear
Invalid
What is the hold condition of a flip-flop?
Both S and R inputs activated
No active S or R input
Only S is active
Only R is active
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
the clock pulse is LOW
the clock pulse is HIGH
the clock pulse transitions from LOW to HIGH
the clock pulse transitions from HIGH to LOW
How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
It can't be done
Invert the Q outputs
Invert the S-R inputs
None of the above
What is one disadvantage of an S-R flip-flop?
It has no Enable input
It has a RACE condition
It has no clock input
It has only a single output
The truth table for an S-R flip-flop has how many VALID entries?
3
1
4
2