21.
Address line for TRAP is?
A
0023H
B
0024H
C
0033H
D
0099H
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100 practice sets · Page 2 of 5
Address line for TRAP is?
0023H
0024H
0033H
0099H
In 8086 microprocessor one of the following statements is not true?
coprocessor is interfaced in max mode.
coprocessor is interfaced in min mode.
I /O can be interfaced in max / min mode.
supports pipelining
In 8086 microprocessor the following has the highest priority among all type interrupts?
NMI
DIV 0
TYPE 255
OVER FLOW
In 8086 the overflow flag is set when _____________.
the sum is more than 16 bits.
signed numbers go out of their range after an arithmetic operation.
carry and sign flags are set.
subtraction
In 8086, Example for Non maskable interrupts are ________.
TRAP
RST6.5
INTR
RST6.6
What is DEN?
direct enable
data entered
data enable
data encoding
ALE stands for ___________
address latch enable
address level enable
address leak enable
address leak extension
8086 and 8088 contains _______ transistors
29000
24000
34000
54000
Expansion for HMOS technology_______
high level mode oxygen semiconductor
high level metal oxygen semiconductor
high performance medium oxide semiconductor
high performance metal oxide semiconductor
In which year, 8086 was introduced?
1978
1979
1977
1981
CS connect the output of ______
encoder
decoder
slave program
buffer
The _______ is used to connect more microprocessor
peripheral device
cascade
I/O devices
control unit
The _______ pin is used to select direct command word
A0
D7-D6
A12
AD7-AD6
__________ generate interrupt signal to microprocessor and receive acknowledge
priority resolver
control logic
interrupt request register
interrupt register
Bits in IRR interrupt are ______
reset
set
stop
start
___________ signal prevent the microprocessor from reading the same data more than one
pipelining
handshaking
controlling
signaling
The primary function of the _____________ is to accept data from I/P devices
multiprocessor
microprocessor
peripherals
interfaces
An _________ is used to fetch one address
internal decoder
external decoder
encoder
register
_____ has certain signal requirements write into and read from its registers
memory
register
both (a) and (b)
control
Memory is an integral part of a _______ system
supercomputer
microcomputer
mini computer
mainframe computer