81.
Which among the following data processing instructions does not use the barrel shifter?
A
ADD R2, R5, R4
B
MOV R5, R4, LSL #2
C
MOV r5, R4, LSR #2
D
MOV r5, R4, ROR #2
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99 practice sets · Page 5 of 5
Which among the following data processing instructions does not use the barrel shifter?
ADD R2, R5, R4
MOV R5, R4, LSL #2
MOV r5, R4, LSR #2
MOV r5, R4, ROR #2
When the processor is executing simple data processing instructions, the pipeline enables one instruction to be completed every clock cycle, this is also called as
Throughput
Latency
Execution
None of the above
When the number of stages in a pipeline increases from 3 to 5, then the
Throughput reduces
Latency reduces
Throughput and latency increases
Throughput increases and latency reduces
When semi-hosting is executed, the debug agent
Suspends program execution
Continues program execution
Both a and b
None of the above
When a transfer is required the APB bus moves into the
hold state
setup state
Rising state
None
When a page is selected for replacement, and its modify bit is set :
a and b
the page is clean
the page has been modified since it was read in from the disk
the page is dirty
When a global variable may be modified by an exception handler, it should be declared as:
Volatile
Constant
Static
Dynamic
What is inter-process communication?
None of the above
Communication within the process
Communication between two processes
Communication between two threads of same process
What are the contents of R1 and R2after MVNR1 R2 are executed, assume R2 is 0x01010101
i) R2 = 0x01100110 ii) R1 = 0x01010101
i) R2 = 0x01010101 ii) R1 = 0x01010101
i) R2 = 0x01010101 ii) R1 = 0x10101010
i) R2 = 0x10101010 ii) R1 = 0x01011101
Vector processor architecture falls under the following computer architecture
MISD
SISD
MIMD
SIMD
Vector Floating Point (VFP) architecture provides............floating point architectures.
None of the above
Single precision
Double precision
Both a and b
Vector Floating Point (VFP) architecture is power efficient because of reduction in...........and...........
All of the above
Instruction bandwidth and Data hazard checking
Instruction bandwidth and pipelining
Data Hazard checking and pipelining
Using only two instructions, add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.
ADD r4, r0, r2 ; ADCS r5, r1, r3 ;
ADD r4, r0, r2 ; ADC r5, r1, r3 ;
ADDS r4, r0, r2 ; ADCS r5, r1, r3 ;
ADD r4, r0, r2 ; ADD r5, r1, r3 ;
Thumb-2 technology enhances the 16 bit Thumb instruction set with
None of the above
Intermixing of 32 bits and 16 bits instructions
Only 32 bits instructions
Only 16 bits instructions
The two I2C signals are..........and............
Parallel address, Parallel clock
Serial data, serial clock
Serial select, serial access
Serial address, parallel data
The priority of a process will.........if the scheduler assigns it a static priority.
None of the above
change
remain unchanged
depend on the operating system
The multi-layer architecture acts as a crossbar switch between............in a AMBA 3 AHB
None of the above
Master and slave
Master and master
Slave and slave
The memory which is used to store acopy of data or instructions stored in larger memories, inside the CPU is called
TLB
Level 1 cache
MMU
Registers
The memory blocks in Main Memory are mapped on to the cache blocks with the help of
None of the above
Hash functions
Vectors
Mapping functions