99 practice sets · Page 3 of 5
If the initial register contents of R0, R1 and R2 were; R0= 0x00000000 , R1= 0x02040608 , R2= 0x10305070 . Assume R0 is the result register, after one of the operations below was performed on R1 and R2, which has been modified to R0 = 0x12345678 What was the operation performed on the contents of R2 and R1?
AND
ORR
BIC
MUL
If the access time of a cache is 1nS, and the access time of a main memory is 15nS, assuming that the Cache hit rate is 0.9 and the total number of accesses are 100; then the average access times of the access with cache and without cache will be..........and...........
250 nS and 1500 nS
250mS and 150 nS
25 nS and 1500nS
250mS and 1500mS
If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.
12 cycles
6 cycles
9 cycles
4 cycles
I2C master features:
Programmable I2C address detection
Clock generation
Stop bit detection
All of the above
How many bits are required to specify the Register operands in anARM7 instruction?
32 bits
16 bits
4 bits
2 bits
How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?
Faster
Slower
No difference
None of the above
Frequency of sampling is called
Sampling rate
Quantization
Modulation
All of the above
Exponent and fraction values for a denormalized number are
0, 0
0 < E < Max, Any bit pattern
All 1?s, Any bit pattern
0, Any non-zero bit pattern
Evaluate the following statements I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current processor mode II. R14 is the link register where the core puts the return address on executing a subroutine III. R15 is the program counter and contains the address of the next instruction to be fetched
All the options are true
I and II are true
II and III are true
I and III are true
Evaluate the following statements and select the appropriate answer given from the choices below. I. Von Neumann Architecture shares common memory for Data and Instructions II. Harvard Architecture has separate physical memories for Data and Instructions
Only I is true
Only II is true
Both I and II are true
None of them is true
Equivalent of Rd = NOT(Rm) this operation is performed by which instruction
MVN
NEG
EOR
TST
ELF means
External Library Format
Executable and Linkable Format
Exclusive Loadable Format
None of the above
Control signals can be categorized by the pipeline stage that uses them. Which one of the following signal could be used in the Execution stage of an instruction?
MemRead
RegWrite
ALUop
PCsrc
Consider a four bit ALU which does four bit arithmetic. When the following four bit numbers are added, what is the status of NZCV flags? 1101 + 1011
NZCV = 0111
NZCV = 1000
NZCV = 1001
NZCV = 1010
Coherence means
Multiple copies of different data are not available at each level of hierarchy.
Multiple copies of same data are available at each level of hierarchy.
Single copy of data is available at only one level of hierarchy.
Multiple copies of different data are available at only one level of hierarchy.
Choose the correct order for default memory map
RW->RO->ZI
ZI->RO->RW
RO->RW->ZI
RO->ZI->RW
Cache memory acts between
CPU and Main Memory
CPU and FPU
MMU and Hard Disk
None of these
Cache design elements are
Block size
Cache size
Mapping functions
All of the above
By default DMA is not a
Master
Slave
Clock
All of the above
An instruction that is used to move data from an ARM Register to a Status Register (CPSR or SPSR) is called
MRC
MRS
MSR
MCS
