Electrical and Electronics : Practice Questions and Answers

In the memory hierarchy, as the speed of memory access increases the memory size

In the ARM Nomenclature ARMxTDMI, D and M stand for

In an Operating System, each process has its own

In a 32- bit IEEE 754 notation, biased value of exponent value ranges from

If Vector Floating Point (VPF) has to handle 8-single precision numbers, VPF architecture must have..........processing elements that work in parallel.

If the Most Significant Byte (MS) is stored first while ordering byte values for storing data in memory, it is called as

If the initial register contents of R0, R1 and R2 were; R0= 0x00000000 , R1= 0x02040608 , R2= 0x10305070 . Assume R0 is the result register, after one of the operations below was performed on R1 and R2, which has been modified to R0 = 0x12345678 What was the operation performed on the contents of R2 and R1?

If the access time of a cache is 1nS, and the access time of a main memory is 15nS, assuming that the Cache hit rate is 0.9 and the total number of accesses are 100; then the average access times of the access with cache and without cache will be..........and...........

If an instruction takes 3 cycles for execution, then how many cycles are needed for executing4 instructions of the same type in a sequence using a 3-stage pipeline? Assume that there are no interrupts or exceptions while executing them.

I2C master features:

How many bits are required to specify the Register operands in anARM7 instruction?

How do Direct Addressing Mode instructions compare with respect to the Indirect Addressing Mode instructions?

Frequency of sampling is called

Exponent and fraction values for a denormalized number are

Evaluate the following statements I. R13 is traditionally used as the stack pointer and stores the head of the stack in the current processor mode II. R14 is the link register where the core puts the return address on executing a subroutine III. R15 is the program counter and contains the address of the next instruction to be fetched

Evaluate the following statements and select the appropriate answer given from the choices below. I. Von Neumann Architecture shares common memory for Data and Instructions II. Harvard Architecture has separate physical memories for Data and Instructions

Equivalent of Rd = NOT(Rm) this operation is performed by which instruction

ELF means

Control signals can be categorized by the pipeline stage that uses them. Which one of the following signal could be used in the Execution stage of an instruction?

Consider a four bit ALU which does four bit arithmetic. When the following four bit numbers are added, what is the status of NZCV flags? 1101 + 1011