1.
The MCLK speed can be reduced to allow access to
A
Faster peripherals
B
Slower peripherals
C
CPU
D
All of the above
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The MCLK speed can be reduced to allow access to
Faster peripherals
Slower peripherals
CPU
All of the above
The main advantage of multiple bus organization over the single bus is
Reduction in the number of cycles for execution
Increase in size of the register
Better connectivity
None of the above
The Logical Instructions are: ORR, EOR, TEQ, AND, TST, BIC, MOV, MVN Why is the V flag unaffected by the logical data processing instructions?
Since V flag and C flag are always the same after any logical operations
Because it will delay the execution of logical operations
V flag is relevant only when an Arithmetic operation is performed
None of the above
The L1 cache is typically split into.........and...........cache for the pipelined system
Instruction, Data
Instruction, Instruction
Data, Data
All of the above
The idea of cache memory exploits the following property of programs
Principle of locality
on the heuristic 90-10 rule
on the fact that references generally tend to be farther
all of the above
The fastest data access is provided using
Caches
DRAM?s
SRAM?s
Registers
The average time required to reach a storage location in memory and obtain its contents is called
Latency time
Access time
Turnaround time
Response time
The amount of time required to read a block of data from a disk into memory is composed of seek time, rotational latency, and transfer time. Rotational latency refers to
the time it takes for the platter to make a full rotation
the time it takes for the read-write head to move into position over the appropriate track
the time it takes for the platter to rotate the correct sector under the head
none of the above
Status of Z flag after the execution of CMP instruction given below, when R0 = 12; R9 = 12; is CMP R0, R9
Z = 1
Z = 0
Same as previous value
None of the above
State whether the following statement is either true or false. We can represent any number in more than one normalized notation.
True Statement
False Statement
State whether the following statement is either true or false. The set associative map technique combines the benefits of the direct and associative mapping techniques.
True Statement
False Statement
State whether the following statement is either true or false. Reset vector is the location of the first instruction executed by the processor when power is applie
This instruction branches to the initialization code.
True Statement
False Statement
State whether the following statement is either true or false. Mantissa and exponent will improve the range and precision respectively.
True Statement
False Statement
State whether the following statement is either true or false. Interrupt signal can stop the execution of an assembly instruction in the middle while it is being executed.
False Statement
True Statement
State whether the following statement is either true or false. Increasing the block size of cache memory is likely to increase performance primarily because programs exhibit spatial locality.
True Statement
False Statement
State whether the following statement is either true or false. In direct mapping, the presence of the block in memory is checked with the help of block field.
True Statement
False Statement
State whether the following statement is either true or false. In a system with Unified cache, access to data in the cache may impact program execution as well.
True Statement
False Statement
State whether the following statement is either true or false. In a multilevel system cache system, the L2 cache may contain data that is not found in L1 cache.
True Statement
False Statement
State whether the following statement is either true or false. Full technical specifications of the target hardware, memory map of the target system may not be available during SW development in most of the cases.
True Statement
False Statement
State whether the following statement is either true or false. Address of any data in cache memory always refers to the address of the data in Main Memory and not the address within the cache.
True Statement
False Statement