101.
The time it takes for a square wave to go from 10% to 90% of its voltage level is called
A
fan-out.
B
rise time.
C
propagation delay.
D
fall time.
Loading practice questions
Browse topic-based Electrical and Electronics practice sets.
1594 practice sets · Page 6 of 80
The time it takes for a square wave to go from 10% to 90% of its voltage level is called
fan-out.
rise time.
propagation delay.
fall time.
The standard 74XX TTL IC family was originally developed in the
1970s.
1960s.
1950s.
1940s.
The propagation delay of standard TTL gates is approximately
2 µsec.
10 nsec.
4 nsec.
1 µsec.
The primary advantage of ECL over TTL is that ECL integrated circuits have
very low power dissipation.
low noise margins.
very short propagation delay times.
both A and C
The output stage of a TTL gate is a special design called a(n)
totem-pole.
DIP.
MSI.
multiemitter.
The output current for a LOW output is called a(n)
exit current.
sink current.
ground current.
fan-out.
The output current capability for a HIGH output condition is called a(n)
source current.
exit current.
sink current.
fan-out.
The original CMOS line of circuits is the
5400 series.
4000 series.
74C00 series.
74HCOO series.
The number of gates that can be connected to a single output without exceeding the current ratings of the gate is called
dissipation.
propagation.
fan-out.
SSI.
The noise margin for a standard TTL gate is
1.0 V.
0.4 V.
1.4 V.
0.8 V.
The minimum output voltage recognized as a HIGH by a TTL gate is
0.8 V.
2.4 V.
5.0 V.
2.0 V.
The minimum input voltage recognized as a HIGH by a TTL gate is
0.8 V.
2.4 V.
2.0 V.
5.0 V.
The maximum output voltage recognized as a LOW by a TTL gate is
2.0 V.
0.8 V.
2.4 V.
0.4 V. 3
The maximum input voltage recognized as a LOW by a TTL gate is
2.4 V.
0.8 V.
0.0 V.
0.4 V.
The maximum current for a LOW output on a standard TTL gate is
16 µA.
40 mA.
100 µA.
16 mA.
The maximum current for a HIGH output on a standard TTL gate is
-10 µA.
-400 µA.
-1 µA.
-10 mA.
The major advantage of TTL logic circuits over CMOS is
lower propagation delay.
the ability to output higher voltages.
more modern design.
very low power consumption.
The major advantage of CMOS logic circuits over TTL is
very low power consumption.
the ability to produce several output voltage levels.
lower propagation delay.
much higher propagation delay.
The lower transistor of a totem-pole output is saturated when the gate output is
HIGH.
LOW.
malfunctioning.
over driven.
The lower transistor of a totem-pole output is OFF when the gate output is
HIGH.
malfunctioning.
LOW.
over driven.