541.
Memory address refers to the successive memory words and the machine is called as
A
word addressable
B
byte addressable
C
bit addressable
D
Terra byte addressable
Loading practice questions
Browse topic-based Electrical and Electronics practice sets.
1594 practice sets · Page 28 of 80
Memory address refers to the successive memory words and the machine is called as
word addressable
byte addressable
bit addressable
Terra byte addressable
Memory access in RISC architecture is limited to instructions
CALL and RET
PUSH and POP
STA and LDA
MOV and JMP
Itanium processor: Which hazard can be circumvented by register rotation?
Control hazards
Data hazards
Structural hazards
None
Interrupts which are initiated by an instruction are
internal
external
hardware
Software
Intel Pentium CPU is a
RISC based
CISC based
Both of the above
None of the above
Intel 8080 microprocessor has an instruction set of 91 instruction. The opcode to implement this instruction set should be at least
3 bit long
5 bit long
7 bit long
9 bit long
Instruction pipelining has minimum stages
4
2
3
6
In immediate addressing the operand is placed
in the CPU register
after opcode in the instruction
in the memory
in the stack
In daisy-chaining priority method, all the devices that can request an interrupt are connected in
parallel
serial
random
none of the above
In a system with a 16 bit address bus, what is the maximum number of 1K byte memory devices it could contain
16
64
256
65536
In a single byte how many bits will be there?
8
16
4
32
How many bits do you think will be adequate to encode individual character in Devnagari script
12
16
64
10
How many address lines are needed to address each memory location in a 2048X 4 memory chip?
10
11
8
12
How does the number of transistors per chip increase according to Moores law?
Quadratically
Linearly
Cubicly
Exponentially
From where interrupts are generated?A
Central processing unitB
Memory chipsC
RegistersD
I/O devices
For a RS flip-flop constructed with NAND gates and input R=1 and s=1 the state is
Memory state
Set state
Reset state
Unused state
For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution ?
ISA
ANSA
Super-scalar
All of the above
Dynamic RAMs are best suited to
slow system
large system
one bit system
none of the above
During the execution of the instructions, a copy of the instructions is placed in the
Register
RAM
System heap
Cache
Data hazards occur when
Greater performance loss
Pipeline changes the order of read/write access to operands
Some functional unit is not fully pipelined
Machine size is limited