Memory access in RISC architecture is limited to instru - Practice (English) | ObjectiveMcq

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Memory access in RISC architecture is limited to instru - Practice (English) | ObjectiveMcq

PracticeElectrical And ElectronicsParallel ProcessingMemory access in RISC architecture ...

Parallel Processing Electrical And ElectronicsEasy

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Memory access in RISC architecture is limited to instructions

Correct Answer:

(C) STA and LDA

Explanation:

STA and LDA

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