1341.
Zero address instruction takes data from
A
top of the stack
B
front of the queue
C
can be a or b
D
none of these
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Zero address instruction takes data from
top of the stack
front of the queue
can be a or b
none of these
zero address instruction also called as
stack based
accumulator based
can be a or b
none of these
Which of the following is not a visible register?
General Purpose Registers
Address Register
Status Register
MAR
Which addressing mode is efficient
Immediate
Register
Indirect
Direct
Two main types of branch instructions are
conditional branch
unconditional branch
logical branch
both a and b
To increase the speed of memory access in pipelining, we make use of
Special memory locations
Special purpose
registers Cache
Buffers
To evaluate an expression using stack based instrcutions, expression is first converted into
prefix
infix
postfix
none of these
The Sun micro systems processors usually follow............architecture.
CISC
ISA
ULTRA SPARC
RISC
The situation wherein the data of operands are not available is called
Structural hazard
Stalk
Deadlock
Data hazard
The RISC processor has a more complicated design than CISC.
TRUE Statement
FALSE Statement
The pipelining process is also called as
Superscalar operation
Assembly line operation
Von Neumann cycle
None of the mentioned
The instructions which after execution transfer control to the next instruction in the sequence are called
control transfer instructions
Sequential control flow & control transfer instructions
none of the mentioned
Sequential control flow instructions
The instructions that transfer the control to some predefined address or the address specified in the instruction are called as
control transfer instructions
sequential control flow & control transfer instructions
none of the mentioned
sequential control flow instructions
The instructions can be categorized as
Arithematic & Logical
Miscellaneous
all of these
Data transfer
The instruction format register to register has a length of
1 byte
3 bytes
4 bytes
2 bytes
The instruction "JUMP" belongs to
control transfer instructions
branch instructions
control transfer & branch instructions
sequential control flow instructions
The fetch and execution cycles are interleaved with the help of
architecture Clock
Special unit
Control unit
Modification in processor
The CISC stands for
Complete Instruction Set Compliment
Computer Indexed Set Components
Complex Instruction set computer
Computer Instruction Set Compliment
The choice of addressing mode governs
Economy
Programming flexibility
all of these
Efficiency
Register Indirect addressing mode is used for
Accessing variables such as arrays
For holding pointer to structure of array
For Push, Pop operation on stack
addressing local variables of functions