61.
Systems that do not have parallel processing capabilities are
A
SISD
B
SIMD
C
MIMD
D
All of the above
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Systems that do not have parallel processing capabilities are
SISD
SIMD
MIMD
All of the above
SPEC stands for,
Standard Performance Evaluation Code.
System Processing Enhancing Code.
System Performance Evaluation Corporation.
Standard Processing Enhancement Corporation.
Processors of all computers, whether micro, mini or mainframe must have
ALU
Primary Storage
Control unit
All of above
Pipelining strategy is called implement
instruction execution
instruction prefetch
instruction decoding
instruction manipulation
Pipe-lining is a unique feature of
RISC
CISC
ISA
IANA
Pipeline implement
fetch instruction
decode instruction
fetch operand
calculate operand
PC Program Counter is also called
instruction pointer
memory pointer
data counter
file pointer
Parallel programs: Which speedup could be achieved according to Amdahls law for infinite number of processors if 5% of a program is sequential and the remaining part is ideally parallel?
Infinite speedup
5
20
50
Parallel processing may occur
in the instruction stream
in the data stream
both[A] and [B]
none of the above
Micro instructions are stored in
computer memory
primary storage
secondary storage
control memory
Memory address refers to the successive memory words and the machine is called as
word addressable
byte addressable
bit addressable
Terra byte addressable
Memory access in RISC architecture is limited to instructions
CALL and RET
PUSH and POP
STA and LDA
MOV and JMP
Itanium processor: Which hazard can be circumvented by register rotation?
Control hazards
Data hazards
Structural hazards
None
Interrupts which are initiated by an instruction are
internal
external
hardware
Software
Intel Pentium CPU is a
RISC based
CISC based
Both of the above
None of the above
Intel 8080 microprocessor has an instruction set of 91 instruction. The opcode to implement this instruction set should be at least
3 bit long
5 bit long
7 bit long
9 bit long
Instruction pipelining has minimum stages
4
2
3
6
In immediate addressing the operand is placed
in the CPU register
after opcode in the instruction
in the memory
in the stack
In daisy-chaining priority method, all the devices that can request an interrupt are connected in
parallel
serial
random
none of the above
In a system with a 16 bit address bus, what is the maximum number of 1K byte memory devices it could contain
16
64
256
65536