21.
Which value has the speedup of a parallel program that achieves an efficiency of 75% on 32 processors?
A
18
B
24
C
16
D
20
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90 practice sets · Page 2 of 5
Which value has the speedup of a parallel program that achieves an efficiency of 75% on 32 processors?
18
24
16
20
Which one of the following is most suitable to make a parity checkerA
AND gateB
OR gateC
Exclusive- OR gateD
None of the above
Which one of the following is a characteristic of CISC (Complex Instruction Set Computer)
Fixed format instructions
Variable format instructions
Instructions are executed by hardware
None of the above
Which of the following require large computer memory?
Imaging
Graphics
Voice
All of the above
Which of the following memories in a computer is volatile?
RAM
ROM
EPROM
ALL
Which of the following is true about interrupts?
They are generated when memory cycles are stolen
They are used in place of data channels
They can be generated by arithmetic operation
They can indicate completion of an I/O operation
Which of the following code is used in present day computing was developed by IBM corporation?
ASCII
Hollerith Code
Baudot code
EBCDIC code
Which of the following bus is used to transfer data from main memory to peripheral device?
DMA bus
Output bus
Data bus
All of the above
Which miss even occurs in infinite caches?
Coherence miss
Capacity miss
Conflict miss
Cold start miss
Which MIMD systems are best scalable with respect to the number of processors?
Distributed memory computers
ccNUMA systems
nccNUMA systems
Symmetric multiprocessors
Which major development led to the production of microcomputers?
Magnetic disks
floppy disks
Logic gates
Integrated Circuits
Which is the fastest storage unit in a usual memory hierarchy?
Cache
Main memory
Hard disk
Register
Which cache miss does not occur in case of a fully associative cache ?
Conflict miss
Capacity miss
Compulsory miss
Cold start miss
Which Algorithm is better choice for pipelining?
Small Algorithm
Hash Algorithm
Merge-Sort Algorithm
Quick-Sort Algorithm
When Performing a looping operation, the instruction gets stored in the
Registers
Cache
System Heap
System stack
When a subroutine is called, the address of the instruction following the CALL instructions stored in/on the
stack pointer
accumulator
program counter
Stack
What is usually regarded as the von Neumann Bottleneck?
Processor/memory interface
Control unit
Arithmetic logical unit
Instruction set
What is the minimum number of flip-flops required in a counter to count 100 pulses?A
FiveB
sevenC
TenD
hundred
What is the control units function in the CPU?
To transfer data to primary storage
to store program instruction
to perform logic operations
to decode program instruction
What is stored in a Translation Lookaside Buffer?
System dumps
Physical addresses
rogram data
Operating system log files