61.
The controller multiplexes the addresses after getting the _____ signal.
A
RESET
B
ACK
C
Request
D
INTR
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The controller multiplexes the addresses after getting the _____ signal.
RESET
ACK
Request
INTR
The chip can be disabled or cut off from an external connection using ______
LOCK
RESET
Chip select
ACPT
The difference in the address and data connection between DRAM’s and SDRAM’s is _______
The usage of more number of pins in SDRAM’s
The usage of a buffer in SDRAM’s
The requirement of more address lines in SDRAM’s
None of the mentioned
In order to read multiple bytes of a row at the same time, we make use of ______
Shift register
Memory extension
Cache
Latch
The reason for the cells to lose their state over time is ________
Use of Shift registers
The lower voltage levels
None of the mentioned
Usage of capacitors to store the charge
Which of the following is the fullform of CISC?
Complete Instruction Sequential Compilation
Complex Instruction Set Computer
Computer Integrated Sequential Compiler
Complex Instruction Sequential Compilation
What is the full form of ISA?
None of the mentioned
International American Standard
International Standard Architecture
Industry Standard Architecture
For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
ISA
All of the mentioned
Super-scalar
ANSA
The small extremely fast, RAM’s all called as ________
Cache
Heaps
Stacks
Accumulators
If the instruction Add RRR3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).
~7
2
~1
4
________ are the different type/s of generating control signals.
Hardwired
Micro-instruction
Micro-programmed
Both Micro-programmed and Hardwired
Both the CISC and RISC architectures have been developed to reduce the ______
All of the mentioned
Cost
Time delay
Semantic gap
In CISC architecture most of the complex instructions are stored in _____
Diodes
CMOS
Register
Transistors
What does VLIW stands for?
Very Large Instruction Word
Very Long Instruction Width
Very Large Instruction Width
Very Long Instruction Word
The VLIW architecture follows _____ approach to achieve parallelism.
SISD
MIMD
MISD
SIMD
In IA-architecture along with the general flags, which of the following conditional flags are provided?
TF
IOPL
IF
All of the mentioned
Which of the following architecture is suitable for a wide range of data types?
IA-32
ASUS firebird
68000
ARM
The IA-system follows which of the following design?
SIMD
RISC
CISC
None of the mentioned
To reduce the memory access time we generally make use of ______
Cache’s
SDRAM’s
Higher capacity RAM’s
Heaps
If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have ______
Imprecise exceptions
None of the mentioned
Generation word
Exception handling