ObjectiveMcq
Print Protected
This page is protected for print. Use the website to view the content.
The controller multiplexes the addresses after getting the _____ signal.
RESET
ACK
Request
INTR
The controller gets the request from the device needing the memory read or write operation and then it multiplexes the address.
The chip can be disabled or cut off from an external connection using ______
LOCK
RESET
Chip select
ACPT
The chip gets enabled if the CS is set otherwise the chip gets disabled.
The difference in the address and data connection between DRAM’s and SDRAM’s is _______
The usage of more number of pins in SDRAM’s
The usage of a buffer in SDRAM’s
The requirement of more address lines in SDRAM’s
None of the mentioned
The SDRAM uses buffered storage of address and data.
In order to read multiple bytes of a row at the same time, we make use of ______
Shift register
Memory extension
Cache
Latch
The latch makes it easy to ready multiple bytes of data of the same row simultaneously by just giving the consecutive column address.
The reason for the cells to lose their state over time is ________
Use of Shift registers
The lower voltage levels
None of the mentioned
Usage of capacitors to store the charge
Since capacitors are used the charge dissipates over time.
Which of the following is the fullform of CISC?
Complete Instruction Sequential Compilation
Complex Instruction Set Computer
Computer Integrated Sequential Compiler
Complex Instruction Sequential Compilation
The CISC machines are well adept at handling multiple BUS organisation.
What is the full form of ISA?
None of the mentioned
International American Standard
International Standard Architecture
Industry Standard Architecture
The ISA is an architectural standard developed by IBM for its PC’s.
For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
ISA
All of the mentioned
Super-scalar
ANSA
In super-scalar architecture, the instructions are set in groups and they’re decoded and executed together reducing the amount of time required to process them.
The small extremely fast, RAM’s all called as ________
Cache
Heaps
Stacks
Accumulators
Cache’s are extremely essential in single BUS organisation to achieve fast operation.
If the instruction Add RRR3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).
~7
2
~1
4
The value will be much lower in case of multiple BUS organisation.
________ are the different type/s of generating control signals.
Hardwired
Micro-instruction
Micro-programmed
Both Micro-programmed and Hardwired
The above is used to generate control signals in different types of system architectures.
Both the CISC and RISC architectures have been developed to reduce the ______
All of the mentioned
Cost
Time delay
Semantic gap
The semantic gap is the gap between the high level language and the low level language.
In CISC architecture most of the complex instructions are stored in _____
Diodes
CMOS
Register
Transistors
In CISC architecture more emphasis is given on the instruction set and the instructions take over a cycle to complete.
What does VLIW stands for?
Very Large Instruction Word
Very Long Instruction Width
Very Large Instruction Width
Very Long Instruction Word
It is the architecture designed to perform multiple operations in parallel.
The VLIW architecture follows _____ approach to achieve parallelism.
SISD
MIMD
MISD
SIMD
The MIMD stands for Multiple Instructions Multiple Data.
In IA-architecture along with the general flags, which of the following conditional flags are provided?
TF
IOPL
IF
All of the mentioned
These flags are basically used to check the system for exceptions.
Which of the following architecture is suitable for a wide range of data types?
IA-32
ASUS firebird
68000
ARM
IA-32 architecture is suitable for a wide range of data types.
The IA-system follows which of the following design?
SIMD
RISC
CISC
None of the mentioned
This system architecture is used to reduce the steps involved in execution by performing complex operations in one step.
To reduce the memory access time we generally make use of ______
Cache’s
SDRAM’s
Higher capacity RAM’s
Heaps
The time required to access a part of the memory for data retrieval.
If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have ______
Imprecise exceptions
None of the mentioned
Generation word
Exception handling
No explanation is available for this question yet.
