141.
An invalid input voltage for a TTL logic gate would be
A
less than 0.8 V.
B
greater than 2.0 V but less than 5.0 V.
C
greater than 2.0 V.
D
between 0.8 V and 2.0 V.
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An invalid input voltage for a TTL logic gate would be
less than 0.8 V.
greater than 2.0 V but less than 5.0 V.
greater than 2.0 V.
between 0.8 V and 2.0 V.
A family of logic devices designed for extremely high speed applications is called
NMOS
ECL
PMOS
TTL
A common means for comparing the propagation delays and the power dissipation of various logic gates is the
fan-out.
power requirements.
speed-power product.
noise margin.
Which specialized device distinguishes the 74LSXX circuits from standard 74XX circuits?
a Schottky diode
a CMOS transistor
a multiemitter transistor
totem-pole output transistor
Which potential problem must be overcome when interfacing TTL to CMOS?
The HIGH output voltage may be too low.
The LOW output voltage may be too high.
The HIGH output voltage may be too high.
The output current may not be sufficient.
Which of the following output levels would not be a valid LOW for a TTL gate?
0.3 V
0.5 V
0.2 V
All are valid.
Which of the following output levels would be a valid HIGH for a TTL gate?
3.0 V
2.6 V
5.1 V
All are valid.
Which of the following levels would not be a valid LOW for a TTL gate?
0.1 V
0.7 V
1.0 V
All are valid.
Which of the following is not a solution to interface problems between CMOS and TTL?
pull-up resistor
pull-down resistor
level-shifter
buffer
Which of the following is not a common logic family used today?
RTL
ECL
TTL
CMOS
Which of the following digital IC logic families is most susceptible to static discharge?
MOS
TTL
RTL
ECL
When setting the voltage for an external device that must interface with an FPGA, you must change the value of
VDDiO
VCCIN
VCCIO
VDDIN
Which of the following is a special type of transistor used in the TTL series to improve speed characteristics?
Brattain
Schottky
Belrus
Shockley
Which of the following is a concern when using CMOS type devices?
fan out
under voltage
mechanical shock
electrostatic discharge
Which of the following input levels would not be a valid HIGH for a TTL gate?
1.8 V
All are valid.
2.4 V
2.1 V
Which of the following are not characteristics of TTL logic gates?
CMOS transistors
Multiemitter transistors
Totem-pole output
Bipolar transistors
Which alteration is made in the manufacture of a TTL gate to create an open-collector output?
The output transistors are missing.
The top output transistor is missing.
The output transistors are replaced by diodes.
The input transistor is replaced by a diode.
When the outputs of several standard TTL gates are connected together, the gate outputs
usually burn out.
produce more voltage.
enable new logic configurations.
produce more fan-out.
When the outputs of several open-collector TTL gates are connected together, the gate outputs
are ANDed together.
produce more voltage.
produce more fan-out.
usually burn out.
When interfacing CMOS to TTL what potential problem must be overcome?
The output current may be too great.
The high voltage may be too low.
There may be insufficient current.
The low output voltage may be insufficient.