Browse topic-based Electrical and Electronics practice sets.
1594 practice sets · Page 73 of 80
State whether the following statement is either true or false. Increasing the block size of cache memory is likely to increase performance primarily because programs exhibit spatial locality.
True Statement
False Statement
State whether the following statement is either true or false. In direct mapping, the presence of the block in memory is checked with the help of block field.
True Statement
False Statement
State whether the following statement is either true or false. In a system with Unified cache, access to data in the cache may impact program execution as well.
True Statement
False Statement
State whether the following statement is either true or false. In a multilevel system cache system, the L2 cache may contain data that is not found in L1 cache.
True Statement
False Statement
State whether the following statement is either true or false. Full technical specifications of the target hardware, memory map of the target system may not be available during SW development in most of the cases.
True Statement
False Statement
State whether the following statement is either true or false. Address of any data in cache memory always refers to the address of the data in Main Memory and not the address within the cache.
True Statement
False Statement
State whether the following statement is either true or false. A high performance bus can be connected to a low performance bus without bridge.
True Statement
False Statement
Stack is a form of
Last In First Out (LIFO)
First In First Out (FIFO)
Both a and b
None of the above
Size of L1 cache compared to that of L2 cache in a system is
Higher
Lower
Same
None of the above
Serial Peripheral Interface bus allows
Half/full
Synchronous
Serial communication with external devices
All of the above
Run time mapping from virtual to physical address is done by
Memory Management Unit
CPU
PCI
None of the above
R1 = 0b1111 , R2 = 0b0101 , BIC R0, R1, R2
R0 = 0b1010
R0 = 0b1111
R0 = 0b0101
R0 = 0b1100
Operating System maintains the page table for
Each data element
Each instruction
Each address
Each process
MRC, MCR are the
Co-processor register transfer instructions
Thumb instructions
Both a and b
Shift instructions
Minimum possible denormalized number representation is possible with single precision IEEE 754 format is
2-126
2-127
2-149
2-128
Memory unit accessed by its content is called
Read only memory
Programmable Memory
Virtual Memory
Associative Memory
Memory management technique in which the OS stores and retrieves data from secondary storage for use in main memory is called
Fragmentation
Paging
Mapping
None of the above
Main advantage of the PWM is that
Power loss in the switching devices is very high
Power loss in the switching devices is very low
No power loss in switching devices
None of the above
Instruction used to Test equality of two 32-bit values in ARM7 is called
TEQ
TST
EOR
None of the above
Instruction used to multiply R5 contents by R4 and to store the result into R6 is called
MUL R6, R5, LSL #2
MUL R6, R5, R4
MUL R6, R5, LSR #2
None of the above
