101.
Which company further developed the study of RISC architecture?
A
Intel
B
Motorola
C
university of Berkeley
D
MIPS
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135 practice sets · Page 6 of 7
Which company further developed the study of RISC architecture?
Intel
Motorola
university of Berkeley
MIPS
Which company developed 16450?
Philips
Intel
National semiconductor
IBM
Which can be supported if the task or process maintains a separate data area for each thread
single thread system
mono thread system
multiple threads
dual threads
Which can be considered as the lower level in the multitasking operating system?
process
task
threads
multi threads
Which are the two main types of processor connection to the motherboard?
sockets and slots
sockets and pins
slots and pins
pins and ports
Which are the serial ports of the IBM PC?
COM1
COM4 and COM1
COM1 and COM2
COM3
Which are the processors based on RISC?
SPARC
80386
MC68030
MC68020
Which allows the UNIX software to be ported using a simple recompilation?
pSOS+
UNIX compatible library
pSOS+m
pOS+kernel
Which allows the parallel development of the hardware and software in the simulation?
high-level language simulation
low-level language simulation
cpu simulator
onboard simulator
Which allows the full duplex synchronous communication between the master and the slave?
SPI
serial port
I2C
parallel port
Which activity is concerned with identifying the task at the final embedded systems?
high-level transformation
compilation
scheduling
task-level concurrency management
What rate can define the timing in the UART?
bit rate
baud rate
speed rate
voltage rate
What is the purpose of address bus?
to provide data to and from the chip
to select a specified chip
to select a location within the memory chip
to select a read/write cycle
What is the main purpose of the memory management unit?
address translation
large storage
reduce the size
provides address space
What is the clock frequency of 8087?
10 MHz
5 MHz
6 MHz
4 MHz
What is CAM stands for?
content-addressable memory
complex addressable memory
computing addressable memory
concurrently addressable memory
What is 80/20 rule?
80% instruction is generated and 20% instruction is executed
80% instruction is executed and 20% instruction is generated
80%instruction is executed and 20% instruction is not executed
80% instruction is generated and 20% instructions are not generated
What happens when 8 bits are transferred in the SPI?
wait statement
ready statement
interrupt
remains unchanged
What happens to the interrupts in an interrupt service routine?
disable interrupt
enable interrupts
remains unchanged
ready state
What does UART stand for?
universal asynchronous receiver transmitter
unique asynchronous receiver transmitter
universal address receiver transmitter
unique address receiver transmitter