21.
If both inputs of an S-R NAND latch are LOW, what will happen to the output?
A
The output would become unpredictable
B
The output will toggle
C
The output will reset
D
No change will occur in the output
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If both inputs of an S-R NAND latch are LOW, what will happen to the output?
The output would become unpredictable
The output will toggle
The output will reset
No change will occur in the output
One example of the use of an S-R flip-flop is as a(n)
Transition pulse generator
Astable oscillator
Racer
Switch debouncer
A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?
AND or OR gates
XOR or XNOR gates
NOR or NAND gates
AND or NOR gates
If an input is activated by a signal transition, it is ________
edge-triggered
toggle triggered
clock triggered
noise triggered
A positive edge-triggered D flip-flop will store a 1 when ________
the D input is HIGH and the clock transitions from HIGH to LOW
the D input is HIGH and the clock transitions from LOW to HIGH
the D input is HIGH and the clock is LOW
the D input is HIGH and the clock is HIGH
A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
CLK = NGT, D = 0
CLK = PGT, D = 0
CLOCK NGT, D = 1
CLOCK PGT, D = 1
Which of the following is correct for a D latch?
The output toggles if one of the inputs is held HIGH
Q output follows the input D when the enable is HIGH
Only one of the inputs can be HIGH at a time
The output complement follows the input when enabled
Which of the following describes the operation of a positive edge-triggered D-type flip-flop?
If both inputs are HIGH, the output will toggle
The output will follow the input on the leading edge of the clock
When both inputs are LOW, an invalid state exists
The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
Which of the following is correct for a gated D-type flip-flop?
The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
The output complement follows the input when enabled
Only one of the inputs can be HIGH at a time
The output toggles if one of the inputs is held HIGH
How many select lines would be required for an 8-line-to-1-line multiplexer?
2
3
4
8
One application of a digital multiplexer is to facilitate:
Data generation
Serial-to-parallel conversion
Parity checking
Data selector
The inputs/outputs of an analog multiplexer/demultiplexer are:
Bidirectional
Unidirectional
Even parity
Binary-coded decimal
One multiplexer can take the place of:
Several SSI logic gates
Combinational logic circuits
Several Ex-NOR gates
Several SSI logic gates or combinational logic circuits
A basic multiplexer principle can be demonstrated through the use of a:
Single-pole relay
DPDT switch
Rotary switch
Linear stepper
Output will be a LOW for any case when one or more inputs are zero for a(n):
OR gate
NOT gate
AND gate
NOR gate
Which of the following logical operations is represented by the + sign in Boolean algebra?
Inversion
AND
OR
Complementation
The output of an OR gate with three inputs, A, B, and C, is LOW when ________.
A = 0, B = 0, C = 0
A = 0, B = 0, C = 1
LA = 0, B = 1, C = 1
All of the above
The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.
A = 1, B = 1, C = 0
A = 0, B = 0, C = 0
A = 1, B = 1, C = 1
A = 1, B = 0, C = 1
A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n):
Ex-NOR gate
OR gate
Ex-OR gate
NAND gate
The Ex-NOR is sometimes called the ________.
Parity gate
Equality gate
Inverted OR
Parity gate or the equality gate